1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more particularly, to a method for fabricating a capacitor having a dielectric layer of a ferroelectric constant or a high dielectric constant, which is suitable for a high-density, high-speed memory device.
2. Discussion of the Related Art
The adoption of various ferroelectric substances for the fabrication of the capacitor dielectric in a semiconductor memory device has enabled development of large-scale memory devices without the refresh requirements of conventional DRAM devices. Among ferroelectric substances, SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT) has recently been the subject of active research, due to its superior fatigue strength, a favorable degree of magnetic susceptibility, and low leakage current properties.
In most cases, platinum is used for the electrodes forming the capacitor. Before and after the evaporation and etching steps for electrode formation, an annealing process is carried out to achieve crystallization and recovery, which improves the dielectric characteristics and magnetization properties of the SBT layer. The annealing process is performed several times repeatedly in a high temperature oxygen atmosphere of 800.degree. C.
Due to the lack of a diffusion-inhibiting layer, which is a thin protective layer capable of withstanding the high temperature oxygen atmosphere of the annealing process, a non-polysilicon plug structure is frequently adopted for interconnection between the substrate and the capacitor's lower electrode.
Such a capacitor structure, however, is not without its problems. For example, to reduce the generation of a platinum residue and polymers during the etching process for forming the upper electrode of the capacitor, titanium nitride is used for the upper electrode as a hard mask, which, undesirably, oxidizes and forms a film of titanium dioxide during the annealing process for recovery of the SBT layer's characteristics after etching. Then, since the titanium dioxide forms a rough and porous surface and exhibits insulation properties, the upper electrode must be completely rid of the titanium dioxide when a contact hole is formed for metal interconnection. In addition, the poor surface conditions of titanium dioxide causes subsequent layer formations, e.g., wiring, to experience lifting when annealing and cleaning processes are performed.
Moreover, in forming the metal interconnection, titanium is deposited atop the platinum upper electrode to attain an ohmic contact between the metal interconnection and the active region of the substrate. The deposited titanium is diffused to the SBT layer and resides along a grain boundary of the platinum (upper electrode) layer, degrading the remnant polarization value of the SBT layer and reducing its fatigue strength. To resolve the diffusion problem, the metal interconnection (wiring) process needs to be performed separately, which requires additional mask fabrication and evaporation and etching steps, making the process very complicated.
Therefore, an improved method for fabricating the capacitor of a semiconductor memory device is needed.